1. Field of the Invention
This invention relates generally to an electronic device, and, more specifically, to performing a filtering process for a delay lock loop circuit.
2. Description of the Related Art
Modern integrated circuit devices are comprised of millions of semiconductor devices, e.g., transistors, formed above a semiconductor substrate, such as silicon. These devices are very densely packed, i.e., there is little space between them. Similarly, densely packed electrically conducting lines may also be formed in the semiconductor substrate. By forming selected electrical connections between selected semiconductor devices and selected conducting lines, circuits capable of performing complex functions may be created. For example, bits of data may be stored by providing electrical current to a plurality of bit lines and an orthogonal plurality of word lines that may be electrically coupled to one or more capacitors in a semiconductor memory.
The semiconductor memory may be a dynamic random access memory, a flash memory, and the like. The semiconductor memory typically comprises an array of memory cells, address decoding circuitry for selecting one, or a group, of the memory cells for reading or writing data, sensing circuitry for detecting the digital state of the selected memory cell or memory cells, and input/output lines to receive the sensed data and convey that information for eventual output from the semiconductor memory. In many cases, the array of memory cells will be sub-divided into several sub-arrays, or subsets, of the complete collection of memory cells. For example, a semiconductor memory having 16 megabits (224 bits) of storage capacity may be divided into 64 sub-arrays, each having 256K (218) memory cells.
Flash memory (sometimes called “flash RAM”) is a type of non-volatile memory that can be erased and reprogrammed in units of memory called blocks. Other types of memory may be erased and rewritten in smaller units, such as units at the byte level, which are more flexible, but slower than the block operations of flash memory. Flash memory is commonly used to hold control code such as the basic input/output system (BIOS) in a personal computer. When BIOS needs to be changed (rewritten), the flash memory can be written in block (rather than byte) sizes, making it faster to update. Applications employing flash memory include digital cellular phones, digital cameras, LAN switches, computers, digital set-up boxes, embedded controllers, and other devices.
Typically, digital systems, such as memory systems, may comprise a delay lock loop that may be used to align the edges of a plurality of digital signals. For example, a delay lock loop circuit may be used to align the rising edge and/or the falling edge of a clock signal based upon a reference clock signal, to produce a synchronized clock signal. Many times, digital signals from multiple sources access one or more memory spaces in a memory unit. It is desirable that these digital signals be synchronized for proper access of memory. Typical delay lock loops comprise a phase detect unit that detects the phase differences between a plurality of signals. The output of the phase detect unit is then used to affect the operation of a filter that adjusts the delay of an output of the delay lock loop. Typical delay lock loop circuits provide a delay block and a delay line (DLL delay line) that implement a delay upon an input clock signal to produce a delayed, output clock signal.
Generally, the delay lock loops (DLL) comprise various logic sections that initiate and terminate the implementation of various delay lines in the delay lock loops. A DLL system may contain various programming or logic-based sections to synchronize various signals, implement various aspects of delay stages, etc. Often, there is state-machine type logic that guides the various portions of the delay lock loop through various states.
Often, a phase detection scheme is provided in the delay lock loop in order to implement various stages of the delays provided by delay lock loop. Various clock signals are monitored to perform such phase detection and based upon certain aspects of clocks, various states of the delay lock loop portions are entered. One problem that occurs with state-of-the-art implementation of delay lock loops include the fact that a noise in the clock that influences the operation of the delay lock loop may cause the various logic sections within the delay lock loops to enter unintended states. For example, when a delay lock loop is configured to shift-left or to shift-right, various portions of a clock may mistakenly cause a phase control signal to prompt a shift in a wrong direction due to noise in a clock. Errors in the clock, such as clock jitters, due to noise, may also cause a termination of an operation of the delay lock loop. Unexpected results resulting from clock jitters may cause the various logic sections in the delay lock loop to exit the delay lock loop state. This could lead to unlocking of various clock signals, which could lead to errors in data transmission. As a result, phase errors may occur and a device using the delay lock loop may malfunction.
The present invention is directed to overcoming, or at least reducing, the effects of, one or more of the problems set forth above.